EFFECTS OF GATE OXIDE SHORTS IN CMOS INVERTER CIRCUIT

Authors

  • Ratan Kumar Debnath Electronics and Communication Engineering Discipline, Khulna University, Khulna-9208, Bangladesh

DOI:

https://doi.org/10.53808/KUS.2000.2.2.0102-se

Keywords:

Gate oxide shorts; Inverter; Breakdown voltage; Realistic model

Abstract

Gate oxide shorts of MOS transistors play a key role to cause logic errors as well as to show unusual behaviour in CMOS logic gate operation. Although it is unintended electrical connections, but it acts as a dominant defect in some CMOS fabrication processes. By using a realistic model, logic operation of the inverter circuit has been evaluated by changing the resistance of the short, power supply and operating temperature. A dynamic circuit simulator (SPICE) provides the necessary data to verify the analysis considering oxide shorts for n- and p-channel transistors.

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References

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Rajsuman, R. and Jayasumana, Y.K., 1987. On accuracy of switch-level modeling of bridging faults in complex gates. Proceedings of Design Automation Conference, pp. 244-250.

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Soden, J.M. and Hawkins, C.F., 1986. Test considerations for gate oxide shorts in CMOS IC’s. IEEE Design Test Computing Magazine, pp. 56-64.

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Published

29-11-2000

How to Cite

[1]
R. K. . Debnath, “EFFECTS OF GATE OXIDE SHORTS IN CMOS INVERTER CIRCUIT”, Khulna Univ. Stud., pp. 257–262, Nov. 2000.

Issue

Section

Science and Engineering

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