EFFECTS OF GATE OXIDE SHORTS IN CMOS INVERTER CIRCUIT

Ratan Kumar  Debnath

doi:10.53808/KUS.2000.2.2.0102-se

Authors

Ratan Kumar Debnath Electronics and Communication Engineering Discipline, Khulna University, Khulna-9208, Bangladesh

DOI:

https://doi.org/10.53808/KUS.2000.2.2.0102-se

Keywords:

Gate oxide shorts; Inverter; Breakdown voltage; Realistic model

Abstract

Gate oxide shorts of MOS transistors play a key role to cause logic errors as well as to show unusual behaviour in CMOS logic gate operation. Although it is unintended electrical connections, but it acts as a dominant defect in some CMOS fabrication processes. By using a realistic model, logic operation of the inverter circuit has been evaluated by changing the resistance of the short, power supply and operating temperature. A dynamic circuit simulator (SPICE) provides the necessary data to verify the analysis considering oxide shorts for n- and p-channel transistors.

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References

Al-Arian, S.A. and Agrawal, D.P., 1987. Physical failures and fault models of CMOS circuits. IEEE Transactions on Circuits and Systems, CAS-34: 269-279.

Hamdy, E., 1988. Dielectric based antifuse for logic and memory IC’s. International Electronic Devices Design Meeting, pp. 292-301.

Hao, H. and McCluskey, E.J., 1993. Analysis of gate oxide short in CMOS circuits. IEEE Transactions on Computers, 42(12): 1510-1516.

Hawkins, C.F. and Soden, J.M., 1985. Electrical characteristics and testing considerations for gate oxide shorts in CMOS ICs. Proceeding of International Test Conference, pp. 544-555.

Rajsuman, R. and Jayasumana, Y.K., 1987. On accuracy of switch-level modeling of bridging faults in complex gates. Proceedings of Design Automation Conference, pp. 244-250.

Segura, J., Rubio, A. and Figueras, J., 1991. Analysis and modelling of MOS devices with gate oxide short failures. International Symposium on Circuits and Systems, pp. 2164-2167.

Soden, J.M. and Hawkins, C.F., 1986. Test considerations for gate oxide shorts in CMOS IC’s. IEEE Design Test Computing Magazine, pp. 56-64.

Syrzycki, M., 1989. Modeling of gate oxide shorts in MOS transistors. IEEE Transactions on Computer Aided Design, 8: 193-202.

Viswessaran, G.S., 1991. The effects of transistor source-to-gate bridging faults in complex CMOS gates. IEEE Journal of Solid-State Circuits, 26: 1715-1729.